1. Field of the Invention
The invention relates to a calibration device for hyper-frequency adjustment of the reference planes of an apparatus for measuring the dispersion parameters of elements of circuits integrated on a substrate, which device comprises, integrated on the same substrate, standard patterns and accesses to these patterns which are compatible with the contacts of two test probes connected to the apparatus.
The invention is used for monolithic integrated circuit technology components (MMIC) operating at hyper-frequencies of between 40 and 80 GHz, for example around 60 GHz, and of the so-called microstrip type.
Microstrip technology is to be understood to mean a type of technology where the integrated circuits are realised on a substrate, a first surface of which receives the circuit itself, comprising active and passive elements, including the transmission lines formed by microstrip conductors, and the second surface of which receives a ground layer. According to this technology, the value of the impedances is linked on the one hand to the physical dimensions of the strips and on the other hand to the thickness of the substrate separating the strip from the ground layer. Moreover, the connection of the ground leads, or ground points, of the first surface to the ground layer on the second surface is realised by way of plated-through holes which are also referred to as via holes. This technology is particularly attractive for the realisation of hyper-frequency integrated circuits operating, for example around 60 GHz or between 40 and 80 GHz, with a very high integration density.
This technology is to be distinguished from the technology which is referred to as the coplanar technology where the integrated circuits occupy only a single surface of a substrate. In that case the hyper-frequency transmission lines are realised by means of two metallic strips which are arranged in parallel in the single plane of the substrate. The value of the impedances is then linked to the dimensions of one of the metallic strips constituting the conductor and the distance separating the latter from the other strip which is connected to ground. In the coplanar technology, the lines can also be formed by a conductor realised between two ground strips. This technology, involving conductors and ground on one and the same surface of the substrate, requires a large surface area and hence is not very suitable for large scale integration.
Therefore, designers of integrated circuits nowadays prefer the microstrip technology for realising hyper-frequency Monolithic Microwave Integrated Circuits (MMICs).
2. Description of the Related Art
From Japanese Patent JP-3243871 of Feb. 21, 1990, it is already known to realise a device for testing a field-effect transistor in order to establish data bases with its hyper-frequency characteristics which can be used for the implementation of devices in microstrip technology.
To this end, the cited document describes a device (shown in FIG. 1a) with a substrate 201 which comprises a first circuit part 202 and a second circuit part 203 which are realised on a surface of the substrate which is referred to as the upper surface.
In the first circuit part 202 there is formed the field effect transistor 204 to be tested, comprising an input zone with a gate G, a ground zone 211 which is connected to the source electrode S, and an output zone which comprises a drain D. The input and output zones comprise transmission lines 205 and 206 and plated-through holes 215 which are connected to the ground layer on the lower surface of the substrate. The assembly formed by a line end situated between two plated-through holes will be referred to hereinafter as "access". The input and output accesses of the transistor 204 to be tested, therefore, are situated on the one hand in the zone 207 formed by the end 214 of the line 205 and the plated-through holes 215, and on the other hand in a symmetrical zone 208 which is formed by the end of the line 206 and the two other plated-through holes. The accesses are thus symmetrically arranged on the upper surface of the substrate, at opposite edges thereof, each access comprising ground-conductor-ground.
In the second circuit part 203 there is implemented a calibration structure which comprises:
two open line portions 220 with respective accesses ground-conductor-ground 216 of the type described above, aligned with the accesses 207 and 208 of the transistor at the edges of the substrate; PA1 two load line portions 222 having accesses 218 of the same type which are aligned with the accesses 207, 208 of the transistor at the edges of the substrate, said lines, however, being symmetrically formed relative to one another. These load lines are formed by segments of microstrip lines having lengths equal to those of the open lines, each of their ends which are remote from those of the accesses comprising a resistance. These resistances are not connected to ground via their other end. The assembly thus constitutes open load lines and the value of the resistances cannot be determined with precision because of the configuration chosen. This part of the calibration structure, therefore, is symmetrical relative to an axis extending parallel to the edges of the substrate and substantially at the level of the gate G of the transistor and at the centre of the upper surface of the substrate. PA1 a) the poor positioning of the reference planes relative to the real input/output zones of the element of the integrated circuit being tested; PA1 b) the poor positioning of the patterns relative to one another so that a saving of space is not achieved at the expense of errors due to undesirable coupling; PA1 c) a poor method of using the calibration circuit due to non-optimum arrangement of the patterns; PA1 d) the lack of perfection in the procedure for bringing the probes into contact with the accesses of the patterns or the elements being tested; PA1 e) the lack of reproducibility in the latter procedure. PA1 is more compact PA1 operates in a wider frequency band PA1 at frequencies which are higher than in the known device. PA1 a short-circuit line and/or an open line and/or a load line, whose accesses are aligned within each series but opposed from one series to another with respect to the zone in which the second ends are situated, their second ends being aligned within each series, defining said facing reference planes, separated by a given distance d, which second ends are also arranged in an offset manner from one series to the other in the plane of the substrate by translations parallel to the reference planes so that the distance between these offset ends is equal to or greater than twice the thickness of the substrate and the distance d separating the reference planes is approximately equal to or smaller than three times the thickness of the substrate.
This calibration structure also comprises a transmission line of 50 .OMEGA., one of its accesses 219 (ground-conductor-ground) being situated at one of the edges of the substrate, its other access 223, being of the same type, not being situated at the other edge but in a zone within the upper surface of the substrate.
This calibration structure thus forms a system which is referred to as a SOLT system (Short, Open, Load, Thru) for on-wafer tests in microstrip technology. It offers the advantage of on-wafer testing, so that the known drawbacks of testing by means of off-wafer calibration structures are avoided.
It is to be noted that the designer of these circuits is confronted by a technical problem concerning the formation of data bases for the different parts of hyper-frequency monolithic integrated circuits.
In order to reduce the cost of manufacturing hyper-frequency integrated circuits, it is necessary to automate their manufacture as much as possible and hence to perform the tests at the completion of assembly. It is desirable to apply test techniques which save the working time normally spent on these tests by a skilled person. This strategy implies that a priori full knowledge must be available concerning the hyper-frequency characteristics of each active or passive element occurring in the ultimate structures of the circuits, as well as knowledge as to how these parameters vary as a function of tolerances in respect of manufacture, polarization or disposition and proximity of these various elements in the circuits.
Generally speaking, the tests are performed by means of an apparatus which is referred to as an automatic vectorial analyser whose accesses are provided with probes connected by way of coaxial cables. The extremities of the probes are of the coplanar ground-conductor-ground type for a flat contact.
In order to use these probes during the tests, the patterns to be tested must have accesses which are also of the type ground-conductor-ground. To this end, as has already been stated, in a microstrip device it is necessary to collect the grounds on the upper surface of the substrate by utilizing pads which are connected to the lower surface, carrying the ground layer, via plated-through holes. Thus, a device constructed in microstrip technology can be tested by means of probes constructed in coplanar technology. This is the case, for example for the device cited as the state of the art.
Calibration of the measuring apparatus is an indispensable operation which consists in bringing the measuring reference layer, which would otherwise be at the level of the output/input accesses of the vectorial analyser, to the level of the inputs/outputs of the pattern being tested, for example a field effect transistor.
Therefore, a calibration structure should comprise patterns of known characteristics such as loads, short-circuits or lines, in order to establish, by calculation, which is the contribution of the measuring apparatus, of the coaxial connection cables, and of the probes themselves, introduced in the measurement of the reflection and transmission coefficients of the matrix S of the hyper-frequency characteristics of the elements of integrated circuits. Therefore, by measuring these coefficients for known patterns, this contribution can be eliminated by calculation (de-embedding), so that the elements of integrated circuits are tested with a high precision.
However, these measurements of the coefficients on known patterns must themselves be very exact. The precision of these preliminary or calibration measurements depends on several factors.
A first, very important factor resides in the quality of the contact of the extremities of coplanar probes with the accesses of the calibration patterns or the elements being tested. It has been found that the device cited as the state of the art exhibits shortcomings in this respect. In the known device, the contact of the probes cannot be checked. A non-detected poor contact could lead to random losses and noise in the measurements.
A second factor which is even more important resides in the reproducibility of the positioning of the extremities of the probe relative to the accesses of the calibration patterns or the elements being tested. In other words, any change in the coverage of the accesses of a pattern by the probe ends causes a change of the impedance and phase and/or module, and hence can cause substantial calibration errors by measurement of incorrect parameters S.
Such positioning errors appear notably when, in order to bring the probe ends into contact with the accesses of the calibration patterns, these probe ends must be displaced. The prior art device has exactly this drawback: the spacing of the probes must be changed so as to move the probes, for example from the short-circuit pattern 220 with the access 216 at the edge of the substrate to the thru pattern 223 with the access 219, one of which is situated at the centre of the surface of the substrate. Such displacements are the source of enormous errors in the measurements of the reflection and transmission coefficients and introduce notably substantial changes of phase which falsify the measurements and lead to very incorrect values of the components of the matrix S to be ultimately calculated.
A third factor resides in the calculation algorithm itself for determining the matrix S, which algorithm is linked to the number and the nature of the calibration patterns. The known device has the drawback that it utilizes an inaccurate algorithm. Actually, the nature of the calibration patterns leads to disturbed amplitude and phase responses of the transmission and reflection coefficients measured, as a function of the frequency, which thus lead to incorrect calculation of the matrix S.
The standard short-circuit (SHORT) exhibits notably an inductance to be measured. Moreover, the open-line standard (OPEN) shows a capacitance. As the frequency increases, the modelling of these standards SHORT and OPEN becomes more and more complex because of the parasitic capacitances and inductances. However, the line LOAD also exhibits a parasitic inductance and reflections which are dependent on the frequency. Moreover, the line THROUGH leads to a characteristic impedance which is not completely real but exhibits an imaginary part. This results in errors in the determination of the various coefficients (S.sub.11, S.sub.22, S.sub.12, S.sub.21) for the calculation of the matrix S which is the object of the calibration. Thus, when the known device is used, the calibration can be performed only within a narrow band and is limited in respect of frequency; therefore, it cannot be applied for frequencies as high as those in the range of from 40 to 80 GHz; this shortcoming is due to the poor definition of the standards.
A fourth factor resides in the positioning of the reference planes after calculations. As has already been stated, the calibration operation aims to bring the reference measuring planes at the level of the input/output zones of the device being tested, that is to say very near one another, for example at a distance of some tens of .mu.m, typically from 50 to 80 .mu.m in the case of a field effect transistor, which planes would otherwise be at the level of the output/input accesses of the vectorial analyser. This calibration operation aims to eliminate the contribution of the probes and the connections of all sorts, including the connections arriving at the element being tested. In the known device, this is not achieved because the reference planes after calculation are remote from the input/output zone of the transistor being tested: the distance between these planes is in the order of 250 .mu.m; consequently, a part of the input/output connections of this transistor must be taken into account. This situation is a source of errors for the measurement of the characteristics of the transistor, because it necessitates the execution of supplementary calculations in order to eliminate the contribution of the connections between the reference planes obtained and the real input/output zones of the transistor.
This situation cannot be avoided in the known device. Actually, the position of the reference planes is, for example defined by the extremity of the open lines 220. The latter lines being arranged opposite one another, there is a gap amounting to at least from two to three times the thickness of the substrate, or 250 .mu.m, which gap cannot be reduced without giving rise to disturbances due to electromagnetic coupling. In the known device the same problem occurs because of the facing position of the loads 222. The position of the reference planes in the device, therefore, is a drawback because the operation for eliminating the external elements from the device being tested is incomplete.
A fifth factor resides in the arrangement of the patterns opposite one another. On the one hand, the calibration circuit comprising the patterns must be as compact as possible in order to reduce the costs, and on the other hand the parts of the patterns may not cause disturbances due to electromagnetic coupling.
In order to reduce the surface area occupied in the known device, the ground via holes of the various accesses are connected in common; the known device is thus rendered compact by saving one via hole out of every two. However, in this case one of the via holes at the end of the line 223, not being situated at the edge but at the centre of the substrate, becomes very close to the load pattern 222. This cannot be avoided because the line 223 is short and the structure is compressed by the common use of the via holes. Nevertheless, this arrangement represents a drawback because electromagnetic coupling occurs between the patterns 222 and 223 and hence calibration errors occur.
For the arrangement of the patterns opposite one another, it is also necessary to take into account the total number of patterns. The known device comprises 8 calibration patterns, which is a large number which evidently occupies a large surface area, resulting in increased costs.
A sixth factor resides in the method of using the calibration structure. It has already been stated that it is important to have available a device whose use involves alignment of the probes with both edges of the substrate. Subsequently, the probes can be lowered so as to apply them to the accesses of the calibration patterns, for each measurement it is only necessary to change the position of the substrate by translation which is exact in respect of magnitude and direction. It has also been stated that the known device does not allow for this type of use, but requires a change of the spacing of the probes at least for one measurement, i.e. that of the line (Thru), resulting in calibration errors.
In the method for using the known calibration device it also occurs that during the measurements relating to one probe, for example that which is positioned on the left-hand accesses, the other probe must be positioned either on the symmetrical accesses at the right or must remain suspended in the air (which is equivalent to an open line). In both cases the measurements are disturbed by electromagnetic coupling which is impossible to quantify. The known calibration structure thus has another drawback.
According to the present state of the art, a very large number of hyper-frequency circuits are realised according to the microstrip technology which is particularly suitable for operation at very high frequencies in the order of from 40 to 80 GHz and for obtaining a high integration density.
The calibration method is a method which contributes to obtaining an exact as possible characterization of the elements being tested. As the element being tested is destined to operate at a higher frequency, the more difficult the measurements will be; nevertheless, they still have to be exact.